The present invention generally relates to semiconductor devices and more particularly to a semiconductor integrated circuit in which a capacitor and a floating-capacitor are integrated on a common substrate.
Semiconductor memory devices are used extensively in various information processing apparatuses and controllers including computers together with logic operation devices such as a microprocessor. Particularly, there is a type of semiconductor memory device called non-volatile semiconductor memory device in which information is stored in a floating gate in the form of electric charges. Typical examples of the non-volatile semiconductor memory device includes EPROMs and flash memory devices. In such a non-volatile semiconductor memory devices, the information is maintained even when the electric power is turned off.
In these days, there is a demand for a so-called mixed integrated circuit in which a flash memory device is integrated with an analog device on a common semiconductor substrate. As it is usual that an analog device includes a capacitor, there is a demand for a technology to form an ordinary capacitor of the analog device and the floating capacitor of the flash memory simultaneously on a common semiconductor substrate.
FIGS. 1A-1F show the fabrication process of a mixed integrated circuit 10 according to a related art in which a flash memory device and an analog capacitor are integrated.
Referring to FIG. 1A, a p-type Si substrate 11 is formed with a field oxide film 12 such that the field oxide film 12 defines a flash memory region 11A and an analog circuit region 11B on the Si substrate 11. In correspondence to analog circuit region 11B, there is formed an n+-type diffusion region 11b in the Si substrate 11 by conducting an ion implantation process of As+ with a dose of 1xc3x971015xe2x88x921016 cmxe2x88x922 while using an acceleration voltage of 50-500 keV. The n+-type diffusion region 11b thus formed serves for a lower electrode of the analog capacitor to be formed.
In the step of FIG. 1A, a tunneling oxide film 11a is formed further on the Si substrate 11 in correspondence to the flash-memory region 11A as a result of thermal oxidation process of the Si substrate 11.
In the step of FIG. 1A, it should further be noted that a polysilicon film is deposited on the Si substrate 11 by a CVD process so as to cover the tunneling oxide film 11a with a thickness of typically 100-150 nm, and a floating gate electrode 13 of the flash-memory device is formed on the flash-memory region 11A as a result of the patterning of the polysilicon film thus formed. Further, an insulation film 14 having an ONO structure, in which an SiN film is vertically sandwiched by a pair of SiO2 films, is formed on the semiconductor structure thus formed with a thickness of 20-30 nm.
Next, in the step of FIG. 1B, a resist pattern 15 is formed on the structure of FIG. 1A and the insulation film 14 is subjected to a dry etching process while using the resist pattern 15 as a mask. As a result of the dry etching process, the insulation film 14 is left only on the flash-memory region 11A as the interlayer insulation film of the flash memory device.
After the foregoing process, the resist pattern 15 is removed and a thermal oxidation process is conducted in the step of FIG. 1C. As a result of the thermal oxidation process, there is formed a gate oxide film 16 on the Si substrate 11. Further, such a thermal oxidation process induces an oxidation in the SiN film constituting the ONO structure, and there is formed a thin oxide film 16A on the insulation layer 14.
As represented in FIG. 1C, the oxidation process is accelerated in the analog circuit region 11B in correspondence to the n+-type diffusion region 11b doped with As, and the thickness of the gate oxide film 16 is increased for a part represented by a reference numeral 16B. The region 16B of the thermal oxide film 16 is used for the capacitor insulation film of the capacitor to be formed.
Next, in the step of FIG. 1D, a composite conductive film of a polysilicon layer and a WSi layer is deposited on the structure of FIG. 1C, and an upper electrode 17B of the analog capacitor is formed on the analog circuit region 11B as a result of the patterning of the conductive film thus formed while using resist patterns 18A and 18B as a mask. The upper electrode 17B thus formed covers the region 16B of the thermal oxide film 16. It should be noted that a control gate electrode 17A is formed simultaneously in the flash-memory region as a result of the foregoing patterning of the conductive film.
Next, in the step of FIG. 1E, a resist pattern 19B is formed on the structure of FIG. 1D so as to cover the analog circuit region 11B, and a resist pattern 19A is formed in the flash-memory region 11A such that the resist pattern 19A covers a part of the control gate electrode 17A. By conducting a dry etching process through the control electrode 17A, the thermal oxide film 16A, the ONO film 14 and the floating gate 13 consecutively while using the resist patterns 19A and 19B as a mask, a gate electrode structure G is formed as represented in FIG. 1E.
Finally, the resist patterns 19A and 19B are removed and an ion implantation process of As+ or P+ is conducted under an acceleration voltage of typically 50-80 keV and a dose of 1xc3x971015xe2x88x921016 cmxe2x88x922 while using the control gate electrode 17A and the upper electrode 17B as a mask. As a result of the ion implantation process, there are formed n-type diffusion regions 11c and 11d in the Si substrate at both lateral sides of the gate electrode structure G. Further, there is formed another diffusion region 11e in the analog circuit region 11B as a result of the foregoing ion implantation process, such that the diffusion region 11e extends from the diffusion region 11b to the field oxide film 12.
In the structure of FIG. 1F, it can be seen that a flash-memory cell having the gate electrode structure G is formed in the flash-memory region 11A defined on the Si substrate 11 and that an analog capacitor C having the diffusion region 11b as the lower electrode, the oxide film 16B as the capacitor insulation film and the polysilicon electrode 17B as the upper electrode, is formed on the same Si substrate 11 in correspondence to the analog circuit region 11B. Thereby, the flash-memory cell and the analog capacitor C are formed substantially simultaneously.
Thus, the foregoing process of the related art enables the formation of a flash memory device and an analog capacitor substantially on the same Si substrate. On the other hand, the capacitor thus formed has a drawback in that the analog circuit cooperating with the analog capacitor is vulnerable to electrical noise propagating through the substrate or change of the substrate bias voltage. As can be seen in FIG. 1F, the lower electrode 11b of the capacitor C is formed in the Si substrate in the form of a diffusion region.
Further, the mixed integrated circuit of the prior art formed according to the process of FIGS. 1A-1F suffers from the problem of increased thickness of the capacitor insulation film 16B, which is caused in the step of FIG. 1C for oxidizing the Si substrate 11 for forming the gate oxide film 16. As noted previously, there occurs an acceleration of oxidation in the diffusion region 11b doped to the n+-type.
It should be noted that the foregoing problem of accelerated oxidation appears conspicuously when conducting the oxidation process at a low temperature by using a wet oxidation technique so as to form the gate oxide film 16 with a uniform thickness. There can be a case in which the thickness of the capacitor insulation film 16B reaches 100 nm when the oxidation process is conducted so as to form the gate oxide film to have a thickness of only 5-10 nm. As a result of the increased thickness of the capacitor insulation film, the analog capacitor thus formed tends to have a reduced capacitance as compared with the designed capacitance value. This means that it is necessary to increase the capacitor area for compensating the decrease of the capacitance caused by the increased thickness of the capacitor insulation film.
In order to avoid the problem of electrical noise in the substrate, there is a proposal to form the analog capacitor on an insulating structure such as the field oxide film 12 formed on the Si substrate 11.
FIGS. 2A-2E show the fabrication process of a semiconductor integrated circuit 20 according to a related art in which the analog capacitor is formed on a field oxide film.
Referring to FIG. 2A, a p-type Si substrate 21 is formed with a field oxide film 22 such that the field oxide film 22 defines a flash memory region 21A. The filed oxide film 22 on the other hand defines an analog circuit region 21B. In the step of FIG. 2A, a tunneling oxide film 21a is formed on the Si substrate 21 in correspondence to the flash-memory region 21A as a result of a thermal oxidation process of the Si substrate 21.
Next, in the step of FIG. 2A, a polysilicon film is deposited on the Si substrate 21 by a CVD process so as to cover the tunneling oxide film 21a with a thickness of typically 100-150 nm. By patterning the polysilicon film thus deposited, there is formed a floating gate electrode 23A of the flash-memory device on the foregoing flash-memory region 21A. Simultaneously, there is formed a polysilicon pattern 23B on the field oxide film 22 as the lower electrode 11b of the analog capacitor. In the step of FIG. 2A, an insulation film 24 having an ONO structure is formed on the structure thus obtained such that the insulation film 24 covers the polysilicon patterns 23A and 23B with a thickness of 20-30 nm.
Next, in the step of FIG. 2B, a thermal oxidation process is conducted on the structure of FIG. 2A and a gate oxide film is formed on the Si substrate 21. Associated with such a formation of the gate oxide film, there is formed a thin oxide film 25 on the insulation film 24 as a result of oxidation of the SiN film constituting the ONO structure. Thereby, it should be noted that the problem of accelerated oxidation in the analog circuit region 21B as in the case of the step of FIG. 1C is effectively avoided due to the fact that the oxide film 25 is formed on the ONO insulation film 24 that extends continuously from the flash-memory region 21A to the analog circuit region 21B. In the step of FIG. 2B, a conductive film 26 is formed further on the oxide film 25 by a CVD process of a polysilicon film and a WSi film such that the conductive film 26 has a total thickness of 300-400 nm.
Next, in the step of FIG. 2C, the conductive film 26 and the underlying oxide film 25 and further the ONO film 24 underneath the oxide film 25 are patterned while using resist patterns 28A and 28B as a mask, and there are formed a capacitor insulation film and an upper electrode pattern 26B of the analog capacitor to be formed on the analog circuit region 21B, wherein the capacitor insulation film is formed of the ONO pattern 24B and the oxide pattern 25B thereon.
At the same time, there is formed a conductor pattern 26A in the flash memory region 21A as a result of the patterning of the conductive film 26. Further, an oxide pattern 25A is formed in the region 21A as a result of the patterning of the oxide film 25 and an ONO pattern 24A is formed as a result of the patterning of the ONO film 24.
Next, in the step of FIG. 2D, a resist pattern 29B is formed on the structure of FIG. 5C such that the resist pattern 29B covers the analog circuit region 21B, and a resist pattern 29A is formed on the control gate electrode 26A in the flash-memory region 21A. Further, the control electrode 26A, the oxide pattern 25A, the ONO pattern 24A and the floating gate pattern 23A underneath are patterned consecutively by a dry etching process while using the resist patterns 29A and 29B as a mask, to form a gate electrode structure G.
Finally, in the step of FIG. 2E, the resist films 29A and 29B are removed, and an ion implantation process of As+ or P+ is conducted under an acceleration voltage of 50-80 keV with a dose of 1xc3x971015-1016 cmxe2x88x922. As a result of the ion implantation process, there are formed n-type diffusion regions 21c and 21d in the Si substrate 21 at both lateral sides of the gate structure G.
In the structure of FIG. 2E, it will be noted that there are formed a flash memory cell and an analog capacitor C respectively on the flash-memory region 21A and on the analog circuit region 31B, wherein the flash memory cell has the gate electrode structure G while the analog capacitor is formed of the lower electrode of the polysilicon pattern 23B on the field oxide film 22, the capacitor insulation film formed of the ONO pattern 24B and the oxide pattern 25B thereon, and the upper electrode of the polysilicon pattern 26B. The flash memory cell and the analog capacitor are formed simultaneously. As the capacitor C is formed on the field oxide film 22, the analog circuit cooperating with the capacitor C is immune to noise or bias voltage change in the substrate 21.
In the semiconductor integrated circuit 20 of FIG. 2E, on the other hand, it should be noted that the capacitor insulation film includes not only the oxide pattern 25B but also the ONO pattern 24B, and thus, the capacitance of the capacitor C becomes inevitably small in the foregoing construction of the related art. In view of the fact that a thickness of 20-30 nm is needed for the ONO pattern 24A for stable operation of the flash-memory, the ONO pattern 24B also has a thickness of 20-30 nm. In a flash-memory, in which a high voltage is applied to the control electrode 26A, it should be noted that a sufficient film thickness is needed for the ONO pattern 24A.
Accordingly, it is a general object of the present invention to provide a novel and useful semiconductor device wherein the foregoing problems are eliminated.
Another and more specific object of the present invention is to provide a semiconductor integrated circuit device including a semiconductor device and a capacitor formed on a common semiconductor substrate, wherein the effect of noise in the semiconductor substrate on the capacitor is eliminated and the capacitance of the capacitor is maximized simultaneously.
Another object of the present invention is to provide a semiconductor integrated circuit comprising:
a substrate defined with a first region and a second region;
a non-volatile semiconductor memory formed on said first region of said substrate;
a capacitor formed on said second region of said substrate;
said non-volatile semiconductor memory including a floating gate electrode formed on said first region, an insulation film formed on said floating gate electrode and a control electrode formed on said insulation film,
said capacitor including a lower electrode formed on said second region of said substrate, a capacitor insulation film formed on said lower electrode, and an upper electrode formed on said capacitor insulation film,
wherein said insulation film and said capacitor insulation film having respective, mutually different thicknesses.
According to the present invention, it is possible to form the insulation film of the non-volatile memory to have a large thickness and capacitor insulation film of the analog capacitor to have a reduced thickness. Thereby, the flash memory can endure application of a high voltage, while the analog capacitor can provide a large capacitance. In the event a high voltage is applied to the analog capacitor, it is also possible to form the capacitor insulation film with a thickness exceeding the thickness of the insulation film of the non-volatile semiconductor memory.
In another aspect, the present invention enables formation of a semiconductor integrated circuit having a flash-memory device and a capacitor on a common substrate substantially simultaneously, such that the capacitor insulation film has a thickness different from the thickness of an insulation film in the flash-memory device. It should be noted that such a change of thickness between the insulation film and the capacitor insulation film can be caused by changing the impurity concentration level between the floating electrode, on which the insulation film is to be formed, and the lower electrode. By forming the analog capacitor such that the analog capacitor is insulated from the substrate, the effect of noise in the semiconductor substrate on the operation of the analog circuit that uses the analog capacitor is minimized.
Another object of the present invention is to provide a method of fabricating a semiconductor device, comprising the steps of:
defining first and second regions on a substrate;
forming a tunneling insulation film on said first region of said substrate;
forming a device isolation film on said second region of said substrate;
forming a first electrode pattern and a second electrode pattern on said substrate substantially simultaneously such that said first electrode pattern covers said tunneling insulation film and such that said second electrode pattern covers said second electrode pattern;
forming a first insulation pattern by forming a first insulation film so as to cover said first electrode pattern and said second electrode pattern and by patterning said first insulation pattern such that said second electrode pattern is exposed;
forming, after said step of forming said first insulation pattern, a second insulation pattern on said second electrode pattern by oxidizing a surface of said exposed second electrode pattern;
depositing, after said step of forming said second insulation pattern, a conductive film on said substrate such that said conductive film covers said first electrode pattern carrying thereon said first insulation pattern and further said second electrode pattern carrying said second insulation pattern; and
patterning said conductive film to form third and fourth electrodes respectively on said first insulation pattern and said second insulation pattern simultaneously.
According to the semiconductor fabrication process of the present invention, it is possible to form the semiconductor integrated circuit such that the insulation film in the non-volatile semiconductor memory has an increased thickness over the capacitor insulation film of the capacitor.
Further, the present invention enables formation of the insulation film and the capacitor insulation film by an oxidation process conducted such that the rate of oxidation is different between the case of forming the insulation film and the case of forming the capacitor insulation film. Thus, it is possible to increase the thickness of the insulation film of the non-volatile semiconductor memory device, which is subjected to application of a high voltage, over the capacitor insulation film, which is required to have a small thickness as possible for increasing the capacitance. Such a change of the oxidation rate is easily achieved by conducting the step of introducing the impurity element by an ion implantation process of P+.
Other objects and further features of the present invention will become apparent from the following detailed description when read in conjunction with the attached drawings.